FEATURED RESEARCH IMAGE
LLM decode memory wall: first bytes/token model
Separating prefill from decode and building a citable traffic ledger for weight reads, KV-cache reads, activation movement, and runtime overhead.
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6 articles
LLM decode memory wall: first bytes/token model
This draft separates prefill from decode and builds a first PCCX traffic ledger for weight reads, KV-cache reads, activation movement, and runtime overhead.
Research Article · Draft · Archive pending · Repro checklist inside · Citation available
FPGA timing closure and the CVO/SFU blocker
This article tracks post-synthesis and post-implementation timing states without turning partial evidence into a timing-clean claim.
Engineering Note · Blocked · Archive pending · Repro checklist inside · Citation available
Runtime readiness as data, not execution
This article represents model, board, and runtime compatibility as deterministic data before any execution path exists.
Methods Note · Merged lane · Archive pending · Repro checklist inside · Citation available
OpenCore to ProCore boundary
This article separates public research artifacts from commercial IP boundaries for ProCore and ASICKit.
Policy Note · Draft · Archive pending · Repro checklist inside · Citation available
Reproducible artifact system
This article defines how public figures and claims map to commits, commands, logs, parsers, checksums, citations, and limitations.
Methods Note · Draft · Archive pending · Repro checklist inside · Citation available
Commercial gates for Evaluation, NRE, ProCore, and ASICKit
This article maps public research artifacts to commercial evidence gates without unsupported production, bitstream, board, timing, or throughput claims.
Commercialization Note · Planning · Archive pending · Repro checklist inside · Citation available